OBJECTIVES 

 To get familiar with MAXPlus II and VHDL

Preparing

Create some directories to keep things organized and have some VHDL code to play with. 

1. Create an ECED 4260 directory 
   1. Create your own directory in the computer
   2. and under your directory, create lab1 directory
2. Now you need to download the two VHDL files that are used in this tutorial, Xor_2.vhd and Xor_3.vhd, make sure you save them to your lab1 directory.  
3. Now start using Maxplus II.

Starting 

Having created directories and downloaded the needed VHDL files, we can start the software package.

1. Start the Maxplus II software by click on Start -> Programs->MAX+plusII 9.23 Baseline-> MAX+plusII 9.23 Baseline
2. Right now you should be looking at Maxplus II, with the Altera Logo in the background of the program.

Editing

1. Open the file containing the Xor_2 by clicking on File menu and selecting Open.
2. File Dialog window will pop-up and click on Xor_2.vhd, then click on the OK button. If you can't see the file make sure you select the All Files option and that you are in the right directory.
3. A text window will pop up with code for the Xor_2 with some color for syntax highlighting.
4. If you need to make changes to the file, then you would do them now but you don't really need to do that right now. Remember to save your work often ( click on the File menu and select Save) and make backups if you are implementing major changes.

Remarks: The name of your VHDL file (e.g. Xor_2.vhd) must the be same as your entity name (e.g. Xor_2). However the name is not case sensitive.

Compiling

1. First thing to do is make the current file (Xor_2.vhd) the current project. To do this, click on File->Project->Set Project to Current File.
2. Now bring up the compiler by clicking on the MAX+plus II menu and selecting Compiler. Notice how your menus changed when you brought up the compiler window, many windows have menus that are specific to them.
3. Now set some options, so click on Interfaces->VHDL Netlist Reader Settings and a dialog box pops up.
4. Notice there are two options, VHDL 87 and VHDL 93,  click on the VHDL 93 option and click OK.
5. Now compile the code, so click on the Compiler window to make it active. If it is hiding behind one of the other windowsclick on the Windows menu and select Compiler.
6. OK, lets compile the code and to do that, click on the Start button ( --drum roll ) and Maxplus II starts to compile your code.
7. When it is done compiling the code, it pops up a dialog with an OK button. Click on the OK button and the dialog disappears.

Remarks: You have successfully compiled the Xor_2, go ahead and compile the Xor_3. Since the Xor_3 uses Xor_2's in its architecture, we had to compile the Xor_2 first so that we could use it. 

8. Follow the steps for opening a file that have been used before but this time select Xor_3.vhd. You will notice that there is quite a few more files than the beginning. 
9. Use the Set Project to Current File menu choice to set Xor_3 as the current project.
10. Bring up the Compiler window and set the option to compile using VHDL 93.
11. To make sure this Xor_3 works, do a functional simulation instead of a back-annotated simulation (i.e. we don't want to include the delays from the chip in our simulation). To do this, make the compiler window active then click on the Processing menu and select Functional SNF Extractor. Notice how the number of blocks in the compiler window decreased because we weren't synthesizing our design for a chip.
12. Start the compilation by clicking on the Start button and then OK when it is done.

Simulating

1. The first thing to do is set up some signals for testing the design. So let us bring up the Waveform Editor, to do this click on the MAX+plus II menu and select Waveform Editor.
2. When the Waveform Editor comes up, there are no signals visible so they have to be added. Make sure the Waveform Editor is active and click on the Node menu and select Enter Nodes from SNF.
3. Click on the List button.
4. In Available Nodes & Groups you will see a list of signals selected. Scroll down till you see three signals with names: |Xor_2:myXor1|Input (I) this is internal signal. They are not interested to us here, so deselect them by holding down the Ctrl key on your keyboard and clicking on this signal. Once you have done that, click on => button to transfer the other signals to the Selected Nodes & Groups box. 
5. Now that you have selected the nodes you want to monitor click on OK.
6. With the nodes added, you will see three signals with their values and a time scale. Right now the time scale is set for 100ns spacing, that is a little too much for us so to change it. Click on the Options menu and select Grid Size, when the box pops up change the value to 10ns and click OK.
7. If you scroll all the way down the time scale you will see it runs until 1us, that is also too much for us so let us change it to something smaller. Click on the File menu (yes isn't it obvious) and select End Time. In the input box change the value to 400ns and click OK.
8. Now to set some values, click on the time scale for Input and select the range from 0ns to 20ns by clicking at 0ns and dragging the mouse to 20ns.
9. After selecting the region, click on the icon with a G in the left toolbar  and enter a value of 0 in the input box then click OK. Now select the region from 20ns to 40ns and set it to 1, select the region from 40ns to 60ns and set it to 2, select the region from 40ns to 60ns and set it to 2, select the region from 60ns to 80ns and set it to 3, select the region from 80ns to 100ns and set it to 4, select the region from 100ns to 120ns and set it to 5, select the region from 120ns to 140ns and set it to 6, select the region from 140ns to 160ns and set it to 7.
10. To repeat this set of values for Input, select the range from 0ns to 160ns and click on the Edit menu and select Copy. Now select the range from 160ns to 320ns and click on the Edit menu and select Paste.
11. In case you haven't guessed yet, grouped signals are represented as Hex values but you can change this by double clicking on the signal name and select the format you want. Do this for Input and set its format to Bin or binary. This will make it easier for us to tell if the Xor is working, right-click on the signal name and select Enter Group and then select the format you want.
    Save the waveform file by clicking on the File menu and selecting Save. The dialog box should have Xor_3.scf in the Filename, now click OK.
12. Now run the simulation, click on the MAX+plus II menu and select Simulator.
13. Click on the Start button and the simulation will start.
14. When the simulation is done, go back to Waveform Editor (if you closed the window click on the Open SCF button in the Simulator window) and the waveform has been updated with the simulation results.
15. Check the Output signal to make sure the Xor is working properly.
16. To print your waveform, click on the File menu and select Print Setup. When the dialog box comes up select Landscape and click OK. Printing your waveform as landscape makes better use of the page. Now to print, click on the File then select Print and click OK when the dialog box comes up. 

lab report
This waveform is required for the report.

Compiling for A Chip

Having made sure our design works, we can start targeting our design for the chip. 

1. Make the compiler window active (click on it or pull it up through the Window menu)
2. Go back to the Processing menu and click on the Functional SNF Extractor which should select the Timing SNF Extractor. Check the Processing menu to make sure there is a check mark next to Timing SNF Extractor.
3. Use a specific FPGA chip in this course so we have to target that chip. Click on the Assign menu and select Device which will bring up the dialog box for choosing our target chip.
4. Check the Device Family and make sure it is set to MAX7000S, if it isn't use the drop down menu to set it to that.
5. Make sure the Show Only Fastest Speed Grades option is unchecked. Sorry folks, we aren't using the speed demons in this class.
6. Scroll through the list of Devices until you find EPM7128SLC84-7, once you found select it and it will show up the Devices box.
7. Click OK.
8. Click on the Start button in the compiler window and watch it go to work.
9. Click OK when it is done.
10. Bring up the simulator window and run the simulation again. You don't need to modify the waveform file.
11. When the simulation is done, open the waveform file by click on the Open SCF button. What do you notice that is different about the Output signal 
    lab report
    Print this waveform. Make note of what is different from the previous waveform.
    
    
12. To check to see how much space the Xor takes in the chip, bring up the compiler window and double click on the rpt icon under the Fitter block. This opens the Compiler Report File for this design.
13. If you scroll down a bit, you will see a diagram of the chip with how the pins were assigned. Scroll further and you will come to a section with a label **Resource Usage** which shows how many pins and logic cells were used.
    lab report
    Print this section of the Complier Report by pasting the text into the editor of your choice.
    
    
14. To see how the design was synthesized , check the Hierarchy Display. Click on the MAX+plus II menu and select Hierarchy Display. We can see the Xor_3 is made up of two Xor's, double click on some of the icons to figure out what they do, note especially the icons with abc.
    lab report
    Print this display. Follow the same steps as printing waveforms
    
    

Using the Graphic Editor

The Graphic Editor is used to draw schematic diagrams of digital systems. A schematic created with this tool can be compiled in the way same as a VHDL file. This tool WILL NOT CREATE VHDL for a given design. This section of the tutorial will teach you how to use the Graphic Editor by having you design a 3 input XOR logic gate.

_{A 3-input XOR logic gate}

The XOR gate can be implemented using AND, OR, and NOT logic gates. The schematic for this design is as follows:


_{Schematic Diagram of a 3-input XOR}

1. From the Max+ plus II menu, select Graphic Editor. This will open a blank Graphic Editor window. Make this the active window.
2. Be sure the Select Tool is the currently selected tool. Click on the icon with the arrow in the left toolbar.
3. Click on the Graphic Editor window, in the approximate center of the empty space.
4. From the Symbol menu, select Enter Symbol. This will bring up a dialog box entitled Enter Symbol. From the Symbol Libraries section, double click on ":\max2plus\lib\prim", which is the logic primitives library. A list will appear in the Symbol files area. In the list, select "and3" and click OK . A symbol for a 3-input AND gate is placed in the Graphic Editor window.
5. Now add the second AND gate. Double click just below the AND symbol (This is a handy shortcut to remember). This brings up the dialog box again. Repeat the previous process to add the second AND gate, and third one and the fourth one.
6. Now add the OR gate. Double click to bring up the dialog box again. Scroll through the Symbol files, select the "or4", and click on OK
7. You also need 3 NOT gates. Double click to the left of the AND gates, select the "not" symbol, and click OK. Repeat this process to add the second NOT gate, and the third one.
8. Lastly, add 3 inputs and 1 output to the design. Using the same procedure as above, add 3 "input" symbols to the left of the NOT gates, and 1 "output" to the right of the OR gate.
9. Rename your inputs and output. Click on the "PIN_NAME" of the top-most input symbol. Type in 'a' as its new name. Now rename the  input symbol 'b' and 'c' for the rest two inputs. Finally, name the output symbol 'out'.
10. Notice you can click and drag the logic symbols around the GE window to obtain a better arrangement for the logic symbols.
11. Now to connect the logic devices. Look in the left toolbar, be sure the "rubberbanding" icon (two black dots connected by a red line) is selected. In the same toolbar, select the Wire Drawing Tool by clicking on the icon with two straight lines joined at a right angle.
12. Connect the gates to match the logic of the schematic above.
13. Save this file as "xor_3.gdf"
    
    lab report
    • Print off the schematic diagram as you would any other file.
    • Use the procedures described in previous sections to compile the design and create a waveform. Simulate all 8 input cases. Confirm that this design functions properly.
    • Print off this waveform

     

    Attention

    Print off Xor_2.vhd and Xor_3.vhd and study them before lab2.

    
    Collect all the print outs and submit your lab report.

Created by Jason Gu

Last Updated: September , 2011