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-- A three input Xor gate
-- Author       : ECED 4260
-- Student ID   : ------
-- Date         : Sept. , 2011
-- File Name	: Xor_3.vhd
-- Architecture : Structural
-- Description  : Three input Xor gate
-- Acknowledgements:
-------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;

entity Xor_3 is
    port (	
		Input  	: in std_logic_vector(2 downto 0);
          	Output  : out std_logic
	);
end Xor_3;



architecture structural of Xor_3 is

component Xor_2
	port( 
		Input 	: in  std_logic_vector(1 downto 0);
		Output 	: out std_logic
	);
end component;

-- Declare the signals needed in the entity
signal internalXorOut  : std_logic_vector(1 downto 0);

begin
	-- Create three Xor_2 components and connect them accordingly

	myXor1: component Xor_2 port map(Input => Input(1 downto 0),
					Output => internalXorOut(0));

	internalXorOut(1) <= Input(2);

	myXor2: component Xor_2 port map(Input => internalXorOut,
					Output => Output);
end structural;