Department of Electrical and Computer Engineering

ECED 4260 IC Design and Fabrication

Lab2 Fundamentals of Digital Design

OBJECTIVES

To get familiar with RTL Implementation , Structural and Behavioral coding of VHDL.

Part I : RTL Implementation

A 2 to one multiplexer has two inputs (a) and (b) as well as a select signal (sel). The truth tables for the operation of a multiplexer is given:

	ab
sel		00	01	11	10
	0	0	0	1	1
	1	0	1	1	0

Use the Graphical Editor to enter the schematic for the MUX_2. Save this file as "MUX_2.gdf" in a lab2 directory.
Compile the MUX_2 follow the lab1 manual.
Test your MUX_2 exhaustively and hand in an annotated waveform with your report.
You will now create the same digital circuit using VHDL. Use this MUX_2 to start and save it as "MUX_2.vhd"
Compile this version of the MUX_2. Test it and hand in an annotated waveform with your report.

Part II : Structural Implementation

For this part of the lab, you will structurally build and test a 4-input MUX using the RTL description of a 2-input MUX as a base component. Use this MUX_4 to start and save it as "MUX_4.vhd".

Draw a top level diagram of the 4-input MUX entity showing inputs and outputs.
Draw a schematic diagram (showing the internal structural architecture) of the 4-input MUX_4, using MUX_2 structure
Compile, and simulate your VHDL code.
Print a waveform that shows the correct operation and annotate this waveform, and include it with your lab report.

Part III : Behavioral Implementation

Build and test a design for a three state Moore machine. The Moore machine is built to detect an non overlapping pattern of "11" with an asynchronous reset. State machines are built using behavioral VHDL. The state diagram for the pattern detector is provided.

Part of the VHDL code is given for the pattern detector ( There are couple errors, you have to fix them to pass the compilation) :

entity PatternDetector is
        port(
                clk, reset, x : in std_logic;
                y           : out std_logic
            );
end PatternDetector;

architecture behavioral of PatternDetector is

        -- Declare a new type for the states and declare
        -- three states
        type state_types is (S0, S1, S2);
        signal state: state_type;

begin

        -- Create a process that handles the state transition
        process (clk, reset)
        begin
                if reset = '1' then
                        state <= S0;
                elseif clk'event and clk = '1' then
                        case state is
                                when S0 =>
                                        if x='1' then
                                                state <= S1;
                                        end if;

                                when S1 =>
                                        if x='1' then
                                                state <= S2;
                                        elsif x='0' then
                                                state <= S0;
                                        end if;

                                when S2 =>
                                        if x='1' then
                                                state <= S1;
                                        elsif x='0' then
                                                state <= S0;
                                        end if;
                        end case;
                end if;
        end process;

        -- Define the outputs based on what state the machine is in.
        with state select
                y       <=      '0'     when    S0,
                                '0'     when    S1,
                                '1'     when    S2;

end behavioral;

Compile and simulate your VHDL code.
Test your state machine and to confirm correct behavior. (When testing the state machine, assign a "clock" value to your clock input in the simulation (use the "C" icon while you are in the Waveform Editor)).
Hand in an annotated waveform

Lab Questions

These questions are to be answered in the body of your lab report:

Describe some of the advantages and disadvantages of structural and behavioral descriptions. Give an example of when you would use a structural description and when you would use a behavioral description.
What test sequence did you use for testing your MUX_4 ? Why is it a sufficient test?

The Report

The report has to include:
1. Your Graphic Editor schematic from Part I (please put down your name onto the schematic before you print the schematic)
2. All your VHDL code
3. Your annotated waveforms for all

Created by Jason Gu

Last Updated: September , 2011