OBJECTIVES 

• To Design and Implement an Arithmetic Logic Circuit

• Integrate a behavioral control path and a structural data path in a single design

• Implement a digital system using MAX+plus II and UP1 boards and observe the operation

Design Problem

Consider the 4-bit Arithmetic Logic Unit (ALU) below:

This design lab will solve the GCD (greatest common divisor) problem.  That is to take two 4-bit unsigned binary numbers, a and b, and compute their greatest common divisor, the largest number that will divide evenly into both numbers. The digital system is implemented on the UP1 boards.

To solve the GCD problem, the following GCD algorithm was used: 

    function gcd(u,v)

           load u and v;

           while u /= v do

              if u > v then

                 u := u - v;

              else

                 v := v - u;

              end if;

           end while;

           output u or v;

        end gcd;

The final digital system should be like this:

1) When the system is first powered up, the user shall press the RESET push button to force the system into initial state. Then the user uses a set of four toggle switches to input the two numbers a and b.  a and b can’t be zero input.

2) The system accepts a when the enter push button is pressed, same as number b.

3) The system calculates the GCD of the two numbers after the two numbers are accepted. Four LEDs labeled L3-L0 display the results.

4) An LED labeled DONE indicates that the first GCD calculation has been computed. Then subsequent GCDs may be computed using the same procedure.

The Lab Assignment

The design will be composed of a distinct control path and data path, which will be put together and programmed into an Altera MAX7128SLC84-7 FPGA.  

Part I: Data Path

There are also some constraints for the data path design. First is that data path should be designed structurally. Second is that behavioral or other explicit comparator operations can not be used within design, and only one 4-bit adder and four two-input XOR gates are allowed within code for the data path.

Two binary numbers are input to the system through four switches. There are three primary operations taking place after the loading of the initial values:

• Comparison of the values u and v.
• Subtraction of one number from another.
• Assignment of the difference to either the u or v register.

The following data path diagram can be derived from the above algorithm:

The algorithm can be distilled into the following processes:

• If the sum of the register v and -u is greater than zero, that sum is placed un-inverted into the v register.
• If the sum of the register v and -u is less than zero, that sum is placed into the u register.
• If the sum is zero, the algorithm is done and the result can be found in either the -u or v registers (since the difference is zero, one result is inverted and the other is not).

Therefore the three operations of comparison, inversion, and assignment are accomplished as follows:

•  Comparison - The comparison result comes from the carry out of the adder. (The zero detection should be fairly obvious).

• Inversion - The 2's complement of a number is found by XOR-ing the number bit-wise with a 1, and then adding a 1 afterwards using the carry in of the adder. 

Assignment - when the sum is presented, it is loaded into one of the u or v registers as the algorithm requires.

As a portion of this lab involves actual implementation of a digital system in hardware, it is important that several important points be made about how to handle this hardware. Large transient voltages such as those present with static electricity can permanently damage the FPGAs. In short, you must take special precautions in handling the UP1 boards and preventing the build up of static electricity on your body. 

The following guidelines will help in greatly reducing the chance of damage to the devices:

Programming the UP1 board with the final design.

1. Ensure that your VHDL code simulates properly before you try programming the UP1 board. It is the EPM7128SLC84-10 device.
2. Also make sure that you did the pin assignments including the clock.
3. The pin outs of the number switches, LEDs, and push buttons can be found on the UP1 Help Sheet.
4. FTP your *.pof file from your design directory onto the local hard drive.
5. You will notice there are two connections that you have to make to your board - the ByteBlaster cable and the power.  The Byte Blaster cable should be on the bench and is connected to the computer you are using to program.
6. Connect the ByteBlaster cable to the UP1 board, and then connect the power from power supply. Use the wires and wire strippers provided in the room to connect power.  Note: do not connect power the wrong way, and align the notch on the ByteBlaster cable with the connector when inserting, or you risk damaging the board.  Check the polarity of the power connection before you try turning on the power supply.
7. Turn on the power supply.  You should see the power light come on.
8. Start MAXplusII from the Programs menu in Windows.
9. Click on the Programmer menu selection under the MAXplusII menu. You should see a new window pop up. Make sure it is selected for the rest of the programming procedure, or you will miss some of the menu items.
10. Click on Multi Device JTAG Chain setup under the JTAG menu. Then choose the device name to be EPM7128S.
11. In the same window, click on the Select Programming File button and choose the top level file name with the .pof extension. Then click on Add which is underneath the Cancel button.
12. In the same window, click on Detect JTAG Chain Info. When this is done, you can click on Ok.  Note: For those of you who don't know, JTAG is a digital test standard (IEEE 1149.1) that happens to be built into the MAX7000 FPGAs. The details of how it works won't be covered here, but it is important that you set this up or programming will not proceed properly.
13. Finally, click on Program in the Programmer Window to program your device. When it is finished, unplug power first and then the ByteBlaster cable.
14. Plug power back into your FPGA and assert Reset. wiring up the FPGA and go through your test cases and see if your board works.

To assign pins on the MAX7128SLC84-7 FPGA use one of the following procedures:

This method of assigning pins is useful if you are planning on assigning all (or most of the signals) in your design, as you can have Maxplus II auto assign the pins and just modify the pin assignments without having to remember the list of external signals that need to be assigned.

1. Assign the device (EPM7128SLC84-7) to your project and compile your design.
2. Click on Assign->Back-Annotate Project and check Chip, Pin & Device and click OK.
3. Click on Assign->Pin/Location/Chip, in the window with the title Existing Pin/Location/Chip Assignments is the list of pins that have been assigned to signals.
4. Select each one and reassign each pin by changing the value in the Pin box and clicking on the Change Button. If  there are any signals in there that shouldn't be (such as test signals you created) then select them and click on the Delete Button. Note that vectors are assigned bit-wise, e.g. a[3..0] is assigned as a3, a2, a1, a0. Make sure all the necessary signals are assigned.
5. Recompile your design and as long as you do not delete your acf file, you will not need to reassign the pins (unless you made a mistake or have to add something).
6. Pin assignments are stored in files with the extension *.acf, if you need to delete files created by Maxplus II, this is one file that you will want to save with your VHDL files and this way you don't have to reassign the pins for your design.

This method of assigning pins is useful if you need to assign only a subset of the external signals (maybe because some of them are test signals and you don't want to assign those).

1. Assign the device (EPM7128SLC84-7) to your project and compile your design.
2. Click on Assign->Pin/Location/Chip
3. In the Node Name box, type in the signal name and the direction of the signal (input or output) will be automatically specified in Pin Type box, make sure this is what you expected. Enter the pin number in the Pin box and click on the Add button. For signals that are vectors, assignment has to be done bit-wise, so for a signal A[3..0] you need to assign pins to A3, A2, A1 and A0.
4. Once you are done entering all your pin assignments click on the OK button.
5. Recompile your design and as long as you do not delete your acf file, you will not need to reassign the pins (unless you made a mistake or have to add something).
6. Pin assignments are stored in files with the extension *.acf, if you need to delete files created by Maxplus II, this is one file that you will want to save with your VHDL files and this way you don't have to reassign the pins for your design.
   

Final Report

1. The preparing elements from Part I and Part II.
2. Your VHDL code from Part I and Part II
3. Your annotated waveforms from Part I and Part II. 
4. Your experimental results from Part III
5. Answer the lab questions in the body of your report if there is any.

Created by Jason Gu

Last Updated: September, 2011